FIGS. 11(a) to 11(f) are sectional views illustrating process steps of producing a T-shaped gate electrode in a conventional production method of a compound semiconductor device. In the figures, reference numeral 1 designates a compound semiconductor substrate, numeral 1a designates a recess, numeral 2 designates an insulating film, numeral 6 designates a gate metal, numeral 6a designates a T-shaped gate electrode, numeral 7 designates a first photoresist film sensitive to electron beam exposure, numeral 8 designates a second photoresist film sensitive to light exposure, and numerals 7a and 8a designate apertures.
Initially, as illustrated in FIG. 11(a), a first photoresist film 7 sensitive to electron beam exposure and a second photoresist film 8 sensitive to light exposure are successively deposited on a compound semiconductor substrate 1. During the deposition, the first photoresist film 7 and the second photoresist film 8 must not mix with each other, more specifically, the resin contained in the first photoresist film 7 must not be dissolved by the solvent contained in the second photoresist film 8. Therefore, photoresists comprising resin and solvents satisfying the above-described condition are selected as the first and second photoresist films 7 and 8.
Then, a prescribed part of the second photoresist film 8 is irradiated with light from an optical exposure apparatus, followed by development of the film 8 using a prescribed developer, forming a first aperture 8a of a relatively large width in the second photoresist film 8 (FIG. 11(b)). Then, a prescribed part of the first photoresist film 7 is irradiated with an electron beam from an electron beam exposure apparatus through the first aperture 8a, followed by development of the film 7 using a prescribed developer, forming a second aperture 7a of a relatively small width (FIG. 11(c)).
Then, as illustrated in FIG. 11(d), using the first and second photoresist films 8 and 7 respectively having the first and second apertures 8a and 7b as a mask, a part of the compound semiconductor substrate 1 is etched away to form a recess 1a. Then, as illustrated in FIG. 11(e), a gate metal 6 is deposited over the entire surface, and the first and second photoresist films 7 and 8 and overlying portions of the gate metal 6 are removed using a lift-off technique, resulting in a T-shaped gate electrode 6a as shown in FIG. 11(f).
FIGS. 12(a)-12(i) illustrate process steps in a method for fabricating a HEMT (High Electron Mobility Transistor) disclosed in Japanese Published Patent Application No. 63-174374 or Electronics Letters 24(1988), p.1327. In the figures, reference numeral 21 designates a GaAs buffer layer, numeral 22 designates an intrinsic type (hereinafter referred to as i type) GaAs layer, numeral 23 designates an n type AlGaAs layer, numeral 24 designates an n.sup.+ type GaAs layer, numerals 25 and 28 designate insulating films, numeral 26 designates a photoresist pattern, numeral 29 designates a refractory metal film, numeral 30 designates a low resistance metal film, and numeral 31 designates an ohmic metal film.
In a HEMT, a region in which electrons travel (an i type GaAs layer of a GaAs HEMT or an i type InGaAs layer of an InP HEMT) is spaced apart from a region which supplies electrons (an n type AlGaAs layer of the GaAs HEMT or a planar doped AlInAs layer of the InP HEMT) by the heterojunction to prevent the electrons from scattering by donor impurities, whereby the electron mobility is increased to insure a high-speed device. In order to increase high frequency characteristics of the HEMT, such as the cut-off frequency (f.sub.t), the maximum oscillation frequency (f.sub.max), and the unilateral gain (U), and to reduce the noise factor (F.sub.0), it is necessary to reduce the gate length, the source resistance, and the gate resistance. In order to improve the reliability of the HEMT, the gate electrode usually comprises a refractory metal.
The production method illustrated in FIGS. 12(a)-12(i) is proposed to improve these characteristics of the HEMT.
Initially, as illustrated in FIG. 12(a), a GaAs buffer layer 21, an i type GaAs layer 22, an n type AlGaAs layer 23, and an n.sup.+ type GaAs layer 24 are successively grown on a semi-insulating GaAs substrate (not shown). Then, a first insulating film 25, such as SiO.sub.2, is deposited on the n.sup.+ type GaAs layer 24 to a thickness of about 3000 .ANG. by plasma CVD, and a photoresist pattern 26 having an aperture of 0.5 .mu.m width is formed on the insulating film 25.
In the step of FIG. 12(b), using the photoresist pattern 26 as a mask, a first aperture 25a is formed in the insulating film 25 by RIE (Reactive Ion Etching) using CHF.sub.3 or CF.sub.4. Thereafter, using the photoresist pattern 26 and the insulating film 25 as a mask, the n.sup.+ type GaAs layer 24 is selectively etched by RIE using a mixture of SiCl.sub.4 and SF.sub.6 that does not etch the n type AlGaAs layer 23 to form a recess 24a. In FIG. 12(b), although opposite side surfaces of the n.sup.+ type GaAs layers 24 exposed in the recess 24a are not etched beyond the aperture 25a, this etching (hereinafter referred to as side etching) is easily carried out by varying the bias voltage during the etching process.
After removing the photoresist pattern 26 using O.sub.2 ashing or an organic solvent, a second insulating film 28, such as SiO.sub.2, is deposited on the upper surface of the insulating film 25 and in the aperture 25a. Preferably, the insulating film 28 is deposited to a thickness of 3000.about.5000 .ANG. by plasma CVD. Thereafter, the insulating film 28 is anisotropically etched by RIE perpendicular to the surface of the substrate, leaving portions 28a on the opposite side surfaces of the insulating film 25 and the GaAs layer 24 (FIG. 12(d)). Thus, a second aperture 28b about 0.25 .mu.m wide is formed between the insulating films 28a.
In the step of FIG. 12(e), a refractory metal film 29 is sputter deposited over the surface to fill the aperture 28a, followed by annealing. Preferably, the refractory metal film 29 comprises WSi. Then, as illustrated in figure 12(f), a low resistance metal film 30 is sputter deposited over the refractory metal film 29. Preferably, the low resistance metal film 30 comprises Ti (500 .ANG.)/Pt (1000 .ANG.)/Au (3000 .ANG.).
In the step of FIG. 12(g), a photoresist pattern 27 is formed on the low resistance metal film 30 and, using this photoresist pattern as a mask, the low resistance metal film 30 is patterned by ion milling and the refractory metal film 29 and the insulating film 25 are patterned by RIE, whereby a gate electrode is produced. During the etching process, the refractory metal film 29 and the insulating film 25 are excessively etched compared to the low resistance metal film 30. FIG. 12(h) illustrates a state where the RIE process is carried out until the insulating film 25 is completely removed.
After removing the photoresist pattern 27, a photoresist pattern for forming source and drain electrodes (not shown) is formed on the substrate, followed by deposition of an ohmic metal, such as AuGe/Ni/Au, and a lift-off process, producing ohmic metal films 31, i.e., spaced apart source and drain electrodes, on the n.sup.+ type GaAs layer 24 (FIG. 12(i)). Thereafter, the substrate is annealed at 400.degree. C. for about two minutes to complete the HEMT.
In the above-described production process, since the gate electrode and the source and drain electrodes are formed self-alignedly, it is possible to reduce the gate length (L.sub.g) and the source resistance (R.sub.s). In addition, since the gate electrode is formed in a T shape, the gate resistance (R.sub.g) is also reduced. Further, since a refractory metal is used for the gate electrode, the reliability of the HEMT is significantly increased. Usually, the reliability is longer than 10.sup.7 hr in normal operation.
In the above-described prior art method of forming the T-shaped gate electrode illustrated in FIGS. 11(a)-11(f), the aperture pattern 7a for determining the width of the lower part of the T-shaped gate electrode, i.e., the gate length, is formed by electron beam exposure of the photoresist film 7 and development of the film. In this pattern exposure method employing electron beam irradiation, since the pattern drawing is carried out from wafer to wafer be irradiating each wafer with an electron beam, it is difficult to improve throughput.
In the prior art method, in order to produce the T-shaped gate electrode with high precision and stability, when the aperture pattern 8a which determines the width of the upper part of the T-shaped gate electrode is formed, i.e., when the photoresist film 8 sensitive to light exposure is developed using a prescribed developer, the photoresist film 7 sensitive to electron beam exposure lying under the photoresist film 8 must not be developed by the developer. Furthermore, when the photoresist film 8 is deposited on the photoresist film 7, these films must not mix with each other. Accordingly, the degree of freedom in selecting photoresist materials is significantly restricted.
Further, in the pattern exposure method using electron beam irradiation (direct drawing method), the resolution limit is 0.2 to 0.25 .mu.m and the gate length cannot be reduced below that limit.
On the other hand, in the prior art production method of illustrated in FIGS. 12(a)-12(i), the first aperture 25a is formed in the insulating film 25, and the insulating side walls 28a are formed on the opposite side surfaces of the aperture 25a to form the second aperture 28b that is narrower than the first aperture 25a, and the gate metal is deposited in the second aperture 28b, whereby the gate length is reduced. Therefore, it is thought that the gate length can be shorter than 0.2.about.0.25 .mu.m if the width of the first aperture 25a of the insulating film 25 is reduced to reduce the size of the second aperture 28b formed between the insulating side walls 28a in the first aperture 25a. However, the width of the first aperture 25a depends on the aperture width of the photoresist pattern 26 which varies in a range of 0.02.about.0.1 .mu.m. This variation in the aperture width of the photoresist pattern 26 directly reflects on the width of the second aperture 28b that determines the gate length. Therefore, in the prior art method, although it is possible to make the gate length shorter than 0.1 .mu.m, the gate length unfavorably varies from wafer to wafer, so that it is difficult to produce a gate electrode having a prescribed gate length below 0.1 .mu.m with high reproducibility.
Further, since the source and drain electrodes are formed self-alignedly with the asymmetric T-shaped gate electrode, the gate-to-source distance is equal to the gate-to-drain distance. If the gate-to-drain distance is increased to attain a high drain breakdown voltage, the gate-to-source distance is also increased, adversely affecting fundamental characteristics of the transistor, such as mutual conductance.